Optimization of the circuit of combined automat IN BASIS NANO-PLA
DOI:
https://doi.org/10.18372/2310-5461.47.14879Keywords:
combined microprogrammed automaton, synthesis, nano-PLA, matrix circuit.Abstract
Nowadays, ASICs (application specific integrated circuit) are widely used for electronic products. One of the problems associated with this basis is to make smaller the area occupied by the circuit of the designed digital system. The solution to this problem allows to reduce the energy that the device circuit consumes, which is especially important for mobile and stand-alone devices.
The aim of the work is to develop a method of synthesis that implements the scheme of a combined microprogramming machine (SMA) and allows one to reduce the number of horizontal buses of nano-PLA up to the value that is typical for an equivalent Moore finite state machine, and, as a result, to make smaller the area of a nano-PLA, using the presence of classes of pseudo-equivalent states (PES) of a Mealy finite state machine . The article considers the example of an automaton synthesis using the proposed method.
Based on the results of studies carried out with using standard examples from the well-known library, the proposed method allows one to make smaller the area of the chip occupied by the automaton circuit by about three times. To achieve such savings, in a general case, it is necessary to jointly fulfill several conditions, namely: each PES class must be represented by one generalized interval of the state coding space, the minimum number of internal variables should be used for encoding the classes, and the state coding should be performed in such a way that each micro-operation was represented by only one term.
Optimal coding of states makes it possible to reduce the number of rows in the table of transitions of the SMA and internal variables. The application of the proposed method, in comparison with the trivial two-level scheme, allows one to make smaller an area of nano-PLA, which implements the SMA scheme in the ASIC basis.
References
Daly D., Fujino L., Smith K. Through the looking glass: Trends in solid-state circuits from the 65th ISSCC. // IEEE Solid-State Circuits Magazine, 2018, V 10, № 10 – pp. 30 – 46.
Smith M. Application Specific Integrated Circuits. – Boston: Addison-Wesley, 1997. – 632pp.
Nababi Z. Embedded Core Design with FPGAs. – New York: McGraw-Hill, 2008. – 418.
DeMicheli G. Synthesis and Optimization of Digital Circuits. – New York: McGraw-Hill, 1994. – 636.
Yuan F. Current-Mode Circuits for Data Communications. – № 4: Springer, 2007. – 416 pp.
S. Baranov, L. Levin, O. Keren, M. Karpovsky. Designing fault tolerant FSM by nano-PLA. – In: Proceeding of 15th International On-Line Testing Symposium, 2009. – Lisbon, pp. 216–220.
Barkalov A., Titarenko L. Logic Synthesis for FSM–based Control Units. –Berlin: Springer,2009 – 233 pp.
Баранов С. И., Скляров В. А. Цифровые устройства на программируемых БИС с матричной структурой. – М.: Радио и связь, 1986. – 272 с.
Baranov S. Logic Synthesis for Control Automata. – Dordrecht: Kluwer Academic Publishers, 1994. – 312 pp.
А.А. Баркалов, Л.А. Титаренко, Я.Е. Визор, А.В. Матвиенко, Горина В.В. Уменьшение числа LUT элементов в схеме совмещенного автомата. // Управляющие системы и машины. – 2016, №3.– С. 16-22.
А.А. Баркалов, Л.А. Титаренко, Я.Е. Визор, А.В. Матвиенко. Синтез совмещенного микро-программного автомата в базисе FPGA. Комп’ютернi засоби, мережi та системи. К.: Ін-т кіберне-тики ім. В.М.Глушкова НАН України, – Київ, 2015 Випуск 14, С. 32-39.
А.А. Баркалов, Л.А. Титаренко, Я.Е. Визор, А.В. Матвиенко. Реализация схемы совмещенно-го микропрограммного автомата в базисе FPGA. – Проблеми інформатизації та управління. Збір-ник наукових праць. Національний авіаційний університет. – Київ, 2015 Випуск 3(51), – С 5-13.
Соловьев В.В. Проектирование цифровых схем на основе программируемых логических инте-гральных схем. – М.: Горячая линия – ТЕЛЕКОМ, 2001. – 636 с.
Sklyarov V., Skliarova I., Barkalov A., Titarenko L. Synthesis and Optimization of FPGA-based Systems. –Berlin: Springer, 2014. – 432 pp.
Barkalov A., Titarenko L., Kolopenczyk M., Mielcarek K., Bazydlo G. Logic Synthesis for FPGA–based Finite State Machines. – Berlin: Springer,2016 – 280pp.
Barkalov A., Titarenko L., Mielcarek K., Chmielewski S. Logic Synthesis for FPGA-based Control Units. –Berlin: Springer, 2020. – 247 pp.
Yang S. Logic Synthesis and optimization benchmarks user guide. Microelectronics Center of North Carolina. – 1991, 43 pp.
