Implementation of a modem with high channel capacity on based the chip CPLD type COOL RUNNER-II

Abstract

The implementation of a modem consisting of two units, a modulator and a de-modulator, is placed in one housing of the XC2C32-3-3 PC44 chip of the Cool Runner-II series, which differs from other CPLDs in high speed and low power consumption. Modem performance (channel bandwidth) is up to 40Mb/s. The modem was developed using the WebPack ISE design system, and a schematic editor was used to describe the general scheme of the project, the State Editor was used to describe the operation of the machines, and the VHDL language was used to describe the encoding table. The validity of the obtained results is confirmed by verification of the developed structure of the modem by the simulation method. As a result of modeling using the ModelSim XE simulation system, we obtained time diagrams of the modem's operation.