MATRIX MULTIPLIER BY MODULO FOR CRYPTOGRAPHIC TRANSFORMATIONS

Authors

DOI:

https://doi.org/10.18372/2410-7840.24.17266

Keywords:

public key cryptosystem, hardware encryption, remainder generator, multiplier

Abstract

The main function of cryptographic methods and means of information protection is to ensure the confidentiality and integrity of data. Data encryption is carried out by specialized means (encryptors), which are based on a certain stable (secure) cryptographic algorithm (symmetric or asymmetric). There are three types of encryptors, that are most widely used for data encryption: hardware, software-hardware and software. Their main difference is not only in the method of encryption and the degree of reliability of data protection, but also it is the price, which often becomes a determining factor for users. Despite the fact that the price of hardware encoders is significantly higher than software, the difference in price is not comparable to a significant improvement in the quality of information protection. Hardware encryption has a number of significant advantages over software encryption, one of which is higher performance. Hardware implementation guarantees the integrity of the encryption process. In this case, the generation and storage of keys, as well as encryption is carried out in the encryption board itself, and not in the computer's RAM. Given this, the development of high-speed operating units of hardware processors for asymmetric encryption, despite their high cost, is an urgent scientific and applied task. This study considers up-to-date approa­ches to multiplication of numbers by modulo. The algorithm of multiplication with stepwise formation of partial and intermediate residues is investigated, which in turn does not require preliminary calculations, and all calculations do not go beyond the range of the bit grid of the module. As a result, a synchronous matrix multiplier was developed, which contains n blocks of schemes I, n-1 FPR and a single FIR with an intermediate residue register. These results will be useful for cryptographic transformation in the systems with high speed and security requirements, for example in critical information infrastructure of the state.

References

Tynymbayev S., Ibraimov M., Namazbayev T., Gnatyuk S. Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems, Eastern-European Journal of Enterprise Technologies, 2022, Vol. 1, Issue 4-115, pp. 37-43.

Айтхожаева Е. Ж., Тынымбаев С. Т. Аспекты аппаратного приведения по модулю в ассиметричной криптографии, Вестник НАН РК, №5, Алматы 2014, С. 88-93.

Gnatyuk S., Iavich M., Kinzeryavyy V., Okhrimenko T., Burmak Y., Goncharenko I. Improved secure stream cipher for cloud computing, CEUR Workshop Proceedings, 2020, Vol. 2732, pp. 183-197,

Карацуба А. А., Офман Ю. П. Умножение многоразрядных чисел на автоматах. ДАН СССР. 1962, Т. 145, С. 293-314.

Cook S. A., Aanderaa S. O. On the minimum computation time of functions, Trans. AMS, 142 (1969), pp. 291-314.

Шенхаге А., Штрассен В. Быстрое умножение больших чисел. Кибернетический сборник. 1973. вып. 2. С. 87-98.

Ковтун М., Ковтун В. Обзор и классификация алгоритмов деления и приведения по модулю больших целых чисел для криптографических приложений [Электронный ресурс] http:// docplayer.ru/ 30670408-Obzor-i-klassifikaciya-algoritmov-deleniya-i-privedeniya-po-modulyu-bolshihcelyh-chisel-dlya-kriptograficheskih-prilozheniy.html

Патент 2029435: МПК Н03М7/18, Петренко В.И., Чипига А.Ф. Комбинационный рекуррентный формирователь остатков: № 5032302 / 24; 20.02. 1995, 3 с.

Патент 2368942: МПК Н03М7/18, Петренко В. Н., Сидорчук А. В., Кузьминов Ю. В. Устройство для формирования остатков по произвольному модулю: №02101066858/08; 27.09.2009, Бюл. № 21, 8 с.

Tynymbayev S.T., Aitkhozhayeva Y.Zh., Adilbekkyzy S. High speed device for modular reduction, Bulletin of National academy of sciences of the Republic of Kazakhstan. 2018. Vol. 6, N 376. P. 147-152.

Патент РК №30983, Тынымбаев С.Т., Айтхожаева Е.Ж. Формирователь остатка по произвольному модулю, 19.02.2016, Бюл. №3

Тынымбаев С.Т., Бердибаев Р.Ш., Омар Т., Шайкулова А.А., Магауин Б. Быстродействующие устройства приведения числа по модулю, Матер. IV Междунар. Азиатской школы-семинара «Проблемы оптимизации сложных систем», Кыргызская Республика, оз. Иссыккуль, пансионат «Отель Евразия». - Ч2, 20-31 июля 2018, С. 273-279.

Barrett, P. (1987). Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor. In: Odlyzko, A.M. (eds) Advances in Cryptology — CRYPTO’ 86. CRYPTO 1986. Lecture Notes in Computer Science, vol 263. Springer, Berlin, Heidelberg. https:// doi.org/10.1007/3-540-47721-7_24

Montgomery P.L. Modular Multiplication without Trial Division, Math. Compulation. Vol. 44, N 170 (Apr., 1985), P. 519-521. DOI: 10.20307/2007970.

Pisek Eran, Henige Thomas M. Method and apparatus for efficient modulo multiplication. Patent US №8Y17756B2, (2013).

S. Tynymbayev, R. Berdibayev, T. Omar, S. Gnatyuk, T. Namazbayev, S. Adilbekkyzy. Devices for multiplying modulo numbers with analysis of the lower bits of the multiplier, Bulletin of National Academy of Sciences of the Republic of Kazakhstan, № 4, 2019, С. 38-45.

Iavich M., Iashvili G., Gnatyuk S., Tolbatov A., Mirtskhulava L. Efficient and Secure Digital Signature Scheme for Post Quantum Epoch, Communications in Computer and Information Science, Vol. 1486, pp. 185-193, 2021.

Published

2023-02-24 — Updated on 2023-02-24

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