Method of reducing the number of LUT elements in the scheme of a composition microprogram control unit with address transformers

Authors

  • Лариса Олександрівна Тітаренко Zelenogursky university, Polska
  • Олександр Миколайович Головін V. M. Glushkov Institute of cybernetics of the National Academy of Sciences of Ukraine
  • Олександр Олександрович Баркалов Zelenogur University, Poland Kharkiv National University of radio electronics
  • Олександр Володимирович Матвієнко V. M. Glushkov Institute of cybernetics of the National Academy of Sciences of Ukraine

DOI:

https://doi.org/10.18372/2310-5461.49.15142

Keywords:

composition microprogram control unit, LUT, EMB, synthesis

Abstract

In advance digital systems, implemented using various VLSI circuits, an important issue remains to reduce the area of the circuit, which is occupied by the control device, and, consequently, reduce the delay time and the amount of power consumption. As a rule, reducing the area of the circuit of the control device allows improving its other characteristics. Methods for solving this problem to some extent depend on the features of the implemented control algorithm and element basis.

The article proposes a method for reducing the number of LUT (Look-Up-Table) elements in the scheme of a composition microprogram control unit (CMCU), based on converting the addresses of the outputs of linear operator circuits (LOC) into output codes. This transformation reduces the number of inputs of the addressing scheme of microinstructions, which is especially important when implementing the circuit of the control device on the FPGA basis due to the small number of inputs of elements of the tabular type LUT. The outputs of the LOC are encoded as elements of some classes of partitioning the set of outputs. This approach allows you to move from a multi-level microinstruction addressing scheme to a two-level one. The control memory and the address conversion block are implemented on embedded memory blocks. The proposed method is an adaptation of the method of double coding of states of Miles automata to the features of CMCU. The method is advisable to use if the microinstruction addressing unit is represented by a multi-level scheme. This is possible if the number of arguments in the memory excitation functions exceeds the number of LUT inputs. If the bit width of the microinstruction address exceeds the number of LUT inputs, then the address converter block circuit is also multilevel. Analysis of standard automata from the library and the Virtex 7 basis showed that this method can be applied to 68% of the library elements. The article considers an example of the synthesis of a CMCU circuit using the proposed method.

Author Biographies

Лариса Олександрівна Тітаренко, Zelenogursky university, Polska

doctor of technical sciences, professor

Олександр Миколайович Головін, V. M. Glushkov Institute of cybernetics of the National Academy of Sciences of Ukraine

candidate of technical sciences

Олександр Олександрович Баркалов, Zelenogur University, Poland Kharkiv National University of radio electronics

doctor of technical sciences, professor

References

Czerwinski R., Kania D. Finite state machines logic synthesis for complex programmable logic devices. Berlin: Springer, 2013. 172 pp.

Skliarova I., Sklyarov V., Sudnitson A. Design of FPGA-based circuits using hierarchical fi-nite state machines. Tallinn: TUT Press, 2012. 240 pp.

DeMicheli G. Synthesis and optimization of digital circuits. New York: McGraw-Hill, 1994. 576 pp.

Tiwari A., Tomko K. Saving power by mapping finite state machines into embedded memory blocks in FPGAs. Proc. Design, Automation and Test in Europe Conference and Exhibition (Paris, France, 6–20 Feb. 2004). 2004. Vol. 2. pp. 916–921.

Баркалов А.А., Титаренко Л.А. Синтез композиционных микропрограммных устройств управления. — Харьков: Коллегиум, 2007. —304 с.

Maxfield C. The design warrior’s guide to FPGAs. Orlando: Academic Press, 2004. 542 pp.

Grout I. Digital systems design with FPGAs and CPLDs. Amsterdam: Elsevier, 2008. 784 p.

Грушницкий Р.И., Мурсаев А.Х., Угрюмов Е.П. Проектирование систем с использова-нием микросхем программируемой логики. СПб: БХВ-Петербург, 2002. 608 с.

Garcia-Vargas I., Senhadji-Navarro R., Jimenez-Moreno G., Civit-Balcells A., Guerra-Gutierrez P. ROM-based finite state machines implementation in low-cost FPGAs. IEEE Intern. Simp. on Industrial Electronics (ISIE’07) (Vigo, 2007). 2007. P. 2342–2347.

White paper FPGA architecture. URL: www.altera.com.

Rawski M., Selvaraj H., Luba T. An application of functional decomposition in ROM-based FSM implementation in FPGA devices. Journal of System Architecture. 2005. Vol. 51, Iss. 6–7. pp. 424–434.

Baranov S. Logic synthesis for control automata. Dordrecht: Kluwer Academic Publishers, 1994. 312 pp.

Sklyarov V., Skliarova I., Barkalov A., Titarenko L. Synthesis and optimization of FPGA-based systems. Berlin: Springer, 2014. 432 pp.

Barkalov A., Titarenko L., Chmielewski S. Mixed encoding of collections of output variables for LUT-based FSMs. Journal of Circuits, Systems and Computers. 2019. Vol. 28, N 8. pp. 1–21.

Barkalov A., Titarenko L. Logic synthesis for FSM-based control units. Berlin: Springer, 2009. 233 pp.

Баркалов А.А., Титаренко Л.А. Преобразование кодов в композиционных микропро-граммных устройствах управления. Кибернетика и системный анализ. 2011. № 5. C. 107–118.

Соловьев В.В. Проектирование цифровых схем на основе программируемых логических интегральных схем. Москва: Горячая линия — ТЕЛЕКОМ, 2001. 636 с.

Баркалов А.А., Титаренко Л.А., Ефименко К.Н. Оптимизация схем композиционных микропрограммных устройств управления. Кибернетика и системный анализ. 2011. № 1. C. 179–188.

Nowicka M., Luba T., Rawski M. FPGA-based decomposition of boolean functions: Algo-rithms and implementations. Proc. of the 6th International Conference on Advanced Computer Sys-tems (Szczecin, 1999). P. 502–509.

Kolopienczyk M., Titarenko L., Barkalov A. Design of EMB-based Moore FSMs. Journal of Circuits, Systems and Computers. 2017. Vol. 21, N 7. P. 1–23.

Vivado Design Suite. https://www.xilinx.com/products/design-tools/vivado.html.

Yang S. Logic synthesis and optimization benchmarks user guide. Version 3.0. Techn. Rep. Microelectronics Center of North Carolina, 1991. 43 p.

Virtex-7 FPGAs. https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html.

Баркалов А.А., Титаренко Л.А., Визор Я.Е., Матвиенко А.В. Оптимальное кодирование состояний в совмещенном автомате. Управляющие системы и машины. 2016. № 6. C. 34–39.

Баркалов А.А., Титаренко Л.А., Визор Я.Е., Матвиенко А.В. Уменьшение числа LUT элементов в схеме совмещенного автомата. Управляющие системы и машины. 2016. № 3. C. 16–22.

Баркалов А.А., Титаренко Л.А., Визор Я.Е., Матвиенко А.В. Уменьшение аппаратур-ных затрат в совмещенных автоматах. Управляющие системы и машины. 2017. № 4. C. 43–50.

Published

2021-03-27

Issue

Section

Information technology, cybersecurity