Application-specific-network-on-chip with link aggregation

Authors

  • Е. В. Короткий Нациоальный технический университет "КПИ"

DOI:

https://doi.org/10.18372/2073-4751.2.6497

Abstract

A method is proposed to reduce the hardware costs of networks-on-chip (NoC) with link aggregation by uneven distribution the number of physical links in aggregated logical connections.  Created application-specific NoC, hardware cost of which is more than two times lower (by 65%), and the maximum operating frequency is by 41% higher than that of the network with homogeneous architecture. As a result of simulation in ModelSim investigated the transport latencies of the proposed solution

References

Angiolini F., Meloni P., Benini L. A layout-aware analysis of networks-on-chip and traditional interconnects for mpsocs // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. – 2007. – Vol.26, №3. – P. 421–434.

Lee H.G., Ogras U.Y., Marculescu R. On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus and network-on-chip approaches // ACM Transactions on Design Automation of Electronic Systems.– 2007.– Vol.12, №3. – P. 1-20.

Dally W., Towles B. Route packets, not wires: on-chip interconnection networks // Proceedings of the 38th annual Design Automation Conference (June 2001). – Las , USA. – P.684-689.

Bjerregaard T., Mahadevan S. A survey of research and practices of network-on-chip // ACM Computing Surveys.– 2006.– Vol.38, №1.– P.1-51.

Atienza D., Angiolini F., Benini L. Network-On-Chip Design and Synthesis Outlook // Integration The VLSI journal.– 2008.– Vol.41, №3.– P.340-359.

Marculescu R., Bogdan P. The Chip Is the Network: Toward a Science of Network-on-Chip Design // Foundations and Trends in Electronic Design Automation. – 2009. – Vol.2, №4. – P.371-461.

Marculescu R., Ogras U. Outstanding Research Problems in NoC Design: System, Microarchitecture and Circuit Perspectives // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.– 2009.– Vol.28, №1.– P.3-21.

Gu H. Survey of dynamically reconfigurable Network-on-chip // in Proc. of International Conference on Future Computer Sciences and Application (June 2011).– Hong Kong, China.– P. 200-203.

Dally W.J. Performance analysis of k-ary n-cube interconnection networks // IEEE Transactions on Computers.– 1990.– Vol.39, №6.– P.775-785.

Dally W.J. Virtual-channel flow control // IEEE Transactions on Parallel and Distributed Systems.– 1992.– Vol.3, №2.– P.194-205.

Korotkiy E.V., Lysenko O.M., Tereshin M.O. Link aggregation in networks-on-chip // Прикладная радиоэлетроника.– 2011.– том 10, № 3.– C. 330-336.

Korotkyi I., Lysenko O. Hardware implementation of link aggregation in networks-on-chip // in Proc. of World Congress on Information and Communication Technologies (Dec.2011).– Mumbai, India.– P.1112-1117.

Mello A., Calazans N., Moraes F. Virtual channels in networks on chip: implementation and evaluation on Hermes NoC // in Proc. of 18th Symposium Integrated Circuits and System Design (2005).– New York, USA.– P.178-183.

Mullins R., West A., Moore S. Low-latency virtual-channel routers for on-chip networks // in Proc. of 31-th International Symposium on Computer Architecture (June 2004).– Munich, Germany.– P.188-197.

Короткий Е.В., Лысенко А.Н. Влияние виртуальных каналов на транспортную задержку сети на кристалле // Проблеми інформатизації та управління.– 2011.– №4.– С. 69-73.

Netmaker.– Режим доступа: http://www.dyn.cl.cam.ac.uk /~rdm34/wiki

Dally W.J., Towles B. Principles and Practices of Interconnection Networks.– San Francisco: Morgan Kaufmann Publishers, 2004.– 550p.

Published

2012-05-23

Issue

Section

Статті