Microcontrollers with stack architecture





FPGA, processor, instruction set, stack architecture, VHDL


The development of microcontroller cores that have both low hardware costs and minimized length of compiled software code that is executed with the required performance is necessary for the implementation of Internet of Things systems, and application specific systems based on field programable gate arrays (FPGA) of small volume.

The main task of the research is to develop an efficient architecture of the microcontroller core, which is configured in a small-volume FPGA.

As a result of the research, it was established that such a kernel should have a stack architecture. Such an architecture minimizes both the size of the compiled software code and hardware costs. In addition, in such an architecture, programs with a large number of conditional instructions, subroutine calls and frequent interruptions are quickly executed.

Eight- and sixteen-bit microcontroller cores with the names SM8 and SM16, respectively, which have a stack architecture, are proposed. Application specific user instructions can be added to the instruction set that are configured to speed up the execution of the executed algorithm. So, it is possible to add to the SM8 core up to dozens of user instructions that are executed by subroutines. A single instruction of the SM16 core calculates the hash function of the input keywords at a rate of two clocks per symbol.

The cores are characterized by low hardware costs and can be configured in FPGAs of various series and manufacturers. In particular, the SM16 core has 1.7 times lower hardware costs and 2.7 times higher performance than the MSP430 architecture core.


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