CORE HARDWARE PARALLELIZING EXECUTION OF PROGRAMS

Abstract

Creating a core that will carry out the instructions of each subroutine in turn , will significantly increase the number of no hardware resources for solving complex problems. This approach saves cycles, the interrupt handler starts executing almost immediately after arrival interrupt , albeit at a lower effective rate, but it allows you to reset the flags or save the results of the periphery faster than you normally would.

The kernel has a set of commands that do not yield sets from existing nuclei can therefore be used in the same areas as the other core. The speed of 1 MIPS per 1 MHz and Availability parallelization enables it to perform complex time-critical program execution. Shows a new way of microcontrollers. Presented architecture can significantly complicate by increasing the number of threads running in parallel, adding new commands and computational units.