DEVICE FOR REDUCING NUMBERS MODULO WITH ANALYSIS OF FOUR-BITS OF SUCH NUMBER PER STEP FOR CRYPTOGRAPHICAL APPLICATIONS - Tynymbayev, Sakhybay; Gnatyuk, Sergiy; Berdibayev, Rat; Polishchuk, Yuliia; Burmak, Yuliia (Ukrainian Information Security Research Journal, 2023)
Today a lot of cyberattacks are directed on the data and other resources of information and communication systems. Cryptography is used to provide confidentiality and integrity of various types of the data (personal, confidentional, sensitive). Symmetric algorithms (block and stream) have high speed parameters to provide data security and privacy in communicational channels. But symmetric ciphers have some problems and disadvantages that must be solved for effective functionning. Modern public key cryptography (asymmetric cryptography) makes it possible not only to encrypt data, but also to solve some current problems of symmetric cryptography – in particular, the problem of distribution of secret keys. However, asymmetric cryptography algorithms are quite slow and resource-intensive, which is why they require the latest approaches to increase performance and optimize their implementation on different platforms. The authors consider the issue of increasing the speed of asymmetric cryptography algorithms and propose a schematic solution (device) for reducing a number by modulus as one of the methods of implementing the summation of integers by modulus. It is known that operations such as multiplication, squaring and modulation affect the performance of cryptographic hardware devices. In particular, the modular operation is the most complex and cumbersome in terms of implementation, which requires special attention of scientists and researchers to develop algorithms and hardware solutions for this problem. From this position, in the paper authors propose to develop and study a device for reducing numbers modulo with the analysis of four digits per step. The developed device was verified by checking the created algorithm for describing the behavioral model in Verilog HDL using time diagrams. The testing showed the correctness of the algorithm of the behavioral model, which confirmed the effectiveness of the developed device for bringing numbers modulo with the analysis of four digits of such a number per step, as well as the possibility of its use for cryptographic applications.